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LT1019 Precision Reference
FEATURES
s s s s s s s s s s s
DESCRIPTIO
Available at 2.5V, 4.5V, 5V, and 10V Plug-In Replacement for Present References Ultra-Low Drift: 3ppm/C Typical Curvature Corrected Series or Shunt Operation Ultra-High Line Rejection: 0.5ppm/V Low Output Impedance: 0.02 Tight Initial Output Voltage: < 0.05% Can Be Heated for Drifts Below 2ppm/C 100% Noise Tested Temperature Output
The LT1019 is a third generation bandgap voltage reference utilizing thin film technology and a greatly improved curvature correction technique. Wafer level trimming of both reference and output voltage combines to produce units with high yields to very low TC and tight initial tolerance of output voltage. The LT1019 can both sink and source up to 10mA and can be used in either the series or shunt mode. This allows the reference to be used for both positive and negative output voltages without external components. Minimum input/ output voltage is less than 1V in the series mode, providing improved tolerance of low line conditions. The LT1019 is available in four voltages: 2.5V, 4.5V, 5V, and 10V. It is a direct replacement for most bandgap references presently available including AD580, AD581, REF-01, REF-02, MC1400, MC1404, and LM168. For ultra-low drift applications (< 2ppm/C), the LT1019 can be operated in a heated mode by driving an internal resistor with an external amplifier. Chip temperature can be externally set for minimum power consumption.
APPLICATI
s s s s s
S
A/D and D/A Converters Precision Regulators Constant Current Sources V/F Converters Bridge Excitation
TYPICAL APPLICATI
15V 357* 0.5W IN OUT 5V
Ultralinear Strain Guage
1.003
OUTPUT VOLTAGE (NORMALIZED) (V)
LT1019-5 GND
350 BRIDGE
R3 2M R2 20k R4 20k
+
A1 LT301A
A2 LT1001
GAIN = 100
-
ACTIVE ELEMENT
R5 2M
R6** 2M
LT1019 * TA01
-5V 357* 0.5W -15V
*REDUCES REFERENCE AND AMPLIFIER LOADING TO 0. **IF R6 = R3, BRIDGE IS NOT LOADED BY R2 AND R4. A1 VOS AND DRIFT ARE NOT CRITICAL BECAUSE A2 ACTS AS A DIFFERENTIAL AMPLIFIER.
U
Output Voltage Drift
1.002 1.001 1.000 0.999 0.998 0.997 -50 -25 LT1019 CURVE 10ppm/C FULL TEMP RANGE "BOX" 5ppm/C 0C TO 70C "BOX" UNCOMPENSATED "STANDARD" BANDGAP DRIFT CURVE 50 25 75 0 TEMPERATURE (C) 100 125
LT1019 * TA02
+
-
UO
UO
1
LT1019 ABSOLUTE AXI U RATI GS
Trim Pin Voltage ................................................... 30V Temp Pin Voltage ..................................................... 5V Heater Voltage Continuous ......................................................... 18V Intermittent (30 sec)........................................... 32V Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C Input Voltage .......................................................... 40V Output Voltage (Note 1) LT1019-5, LT1019-10 ........................................ 16V LT1019-2.5, LT1019-4.5 ...................................... 7V Output Short-Circuit Duration (Note 1) VIN < 20V .................................................... Indefinite 20V VIN 35V ............................................. 10 sec
PACKAGE/ORDER I FOR ATIO
TOP VIEW NC* 8 NC* 1 INPUT 2 TEMP 3 4 GND (CASE) H PACKAGE 8-LEAD TO-5 METAL CAN *INTERNALLY CONNECTED. DO NOT CONNECT EXTERNALLY
TJMAX = 150C, JA = 150C/ W, JC = 45C/W
7
HEATER 6 OUTPUT
5
TRIM
ORDER PART NUMBER LT1019AMH-10 LT1019MH-10 LT1019ACH-10 LT1019CH-10 LT1019AMH-5 LT1019MH-5 LT1019ACH-5 LT1019CH-5 LT1019AMH-4.5 LT1019MH-4.5 LT1019ACH-4.5 LT1019CH-4.5 LT1019AMH-2.5 LT1019MH-2.5 LT1019ACH-2.5 LT1019CH-2.5
ELECTRICAL CHARACTERISTICS
SYMBOL TC PARAMETER Output Voltage Tolerance Output Voltage Temperature Coefficient (Note 2) Line Regulation (Note 3) Ripple Rejection CONDITIONS
VIN = 15V, IOUT = 0, TJ = 25C, unless otherwise noted.
MIN
q q q q
LT1019C (0C to 70C) LT1019M (- 55C to 125C) LT1019I (- 40C to 85C) (VOUT + 1.5V) VIN 40V 50Hz f 400Hz
VOUT VIN RR
2
U
U
W
WW
U
W
TOP VIEW NC* 1 INPUT 2 TEMP 3 GND 4 N8 PACKAGE 8-LEAD PLASTIC DIP 8 7 6 5 NC* HEATER OUTPUT TRIM
S8 PACKAGE 8-LEAD PLASTIC SOIC
*INTERNALLY CONNECTED. DO NOT CONNECT EXTERNALLY.
TJMAX = 100C, JA = 130C/ W (N) TJMAX = 100C, JA = 130C/ W (S)
ORDER PART NUMBER LT1019ACN8-10 LT1019CN8-10 LT1019CS8-10 LT1019IN8-10 LT1019ACN8-5 LT1019CN8-5 LT1019CS8-5 LT1019IN8-5 LT1019ACN8-4.5 LT1019CN8-4.5 LT1019CS8-4.5 LT1019IN8-4.5 LT1019ACN8-2.5 LT1019CN8-2.5 LT1019CS8-2.5 LT1019IN8-2.5
S8 PART MARKING 1910 1905 1945 1925
LT1019A TYP MAX 0.002 3 5 0.5 1.0 0.05 5 10 3 5
MIN
LT1019 TYP 0.02 5 8 5 0.5 1.0
MAX 0.2 20 25 20 3 5
UNITS % ppm/C ppm/C ppm/C ppm/V ppm/V dB dB
q
90 84
110
90 84
110
LT1019
ELECTRICAL CHARACTERISTICS
SYMBOL VOUT IOUT PARAMETER Load Regulation Series Mode (Notes 3, 4) Load Regulation, Shunt Mode Thermal Regulation (Note 6) IQ Quiescent Current Series Mode Minimum Shunt Current Minimum Input/Output Voltage Differential Trim Range (Note 7) IOUT 1mA IOUT = 10mA LT1019-2.5 LT1019-5 LT1019-10 2V VIN 35V CONDITIONS 0 IOUT 10mA*
VIN = 15V, IOUT = 0, TJ = 25C, unless otherwise noted.
MIN
q
LTC1019A TYP MAX 0.02 0.05 0.08 0.4 0.8 0.5 1.0 1.3 0.8 1.1 1.3
MIN
LTC1019 TYP MAX 0.02 0.05 0.08 0.4 0.8 0.5 1.2 1.5 0.8 1.1 1.3
UNITS mV/mA () mV/mA () mV/mA () mV/mA () ppm/mW mA mA mA V V % % %
1mA ISHUNT 10mA (Notes 4, 5) 2.5V, 4.5V, 5V 10V P = 200mW, t = 50ms
q q
0.1 0.1 0.65
0.1 0.1 0.65 0.5 0.9 3.5 3.5 3.5 6 5, - 13 5, - 27 400 25 2.5 2.5
q q q q
0.5 0.9 3.5 6 3.5 5, - 13 3.5 5, - 27 300 400 25 2.5 2.5
Heater Resistance ISC en Short-Circuit Current Output Connected to GND Output Voltage Noise (Note 9)
q
500 50 4
300 15 10
500 50 4
mA mA ppm (RMS) ppm (P-P)
15 10
10Hz f 1kHz 0.1Hz f 10Hz
The q denotes specifications which apply over the full operating temperature range. Note 1: These are high power conditions and are therefore guaranteed only at temperatures equal to or below 70C. Input is either floating, tied to output, or held higher than output. Note 2: Output voltage drift is measured using the box method. Output voltage is recorded at TMIN, 25C, and TMAX. The lowest of these three readings is subtracted from the highest and the resultant difference is divided by (TMAX - TMIN). Note 3: Line regulation and load regulation are measured on a pulse basis with low duty cycle. Effects due to die heating must be taken into account separately. See thermal regulation and application section. Note 4: Load regulation is measured at a point 1/8" below the base of the package with Kelvin contacts. Note 5: Shunt regulation is measured with the input floating. This parameter is also guaranteed with the input connected (VIN - VOUT) > 1V, 0mA ISINK 10mA. Shunt and sink current flow into the output.
Note 6: Thermal regulation is caused by die temperature gradients created by load current or input voltage changes. This effect must be added to normal line or load regulation. Note 7: Minimum shunt current is measured with shunt voltage held 20mV below the value measured at 1mA shunt current. Note 8: Minimum input/output voltage is measured by holding input voltage 0.5V above the nominal output voltage, while measuringVIN - VOUT. Note 9: RMS noise is measured with a single highpass filter at 10Hz and a 2-pole lowpass filter at 1kHz. The resulting output is full-wave rectified and then integrated for a fixed period, making the final reading an average as opposed to RMS. A correction factor of 1.1 is used to convert from average to RMS, and a second correction of 0.88 is used to correct the non-ideal bandpass of the filters.
3
LT1019
TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current (LT1019-2.5)
1.6 1.4 1.2
CURRENT (mA) CURRENT (mA)
1.6 1.4 1.2
1.0 0.8 0.6 0.4 0.2 0 0 5 10
125C 25C -55C
1.0 0.8 0.6 0.4 0.2
125C 25C -55C
CURRENT (mA)
25 30 35 INPUT VOLTAGE (V)
15
20
Minimum Input/Output Voltage Differential
10
2.0 1.5 OUTPUT CURRENT (mA)
OUTPUT CHANGE (mV)
INPUT VOLTAGE/OUTPUT VOLTAGE (dB)
7.5
5.0 TJ = 125C 2.5 TJ = -55C TJ = 25C
0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 INPUT/OUTPUT VOLTAGE (V)
LT1019 * TPC04
Shunt Mode Characteristics (LT1019-2.5)
1.0 0.9 0.8 0.7
CURRENT (mA)
INPUT OPEN
CURRENT (mA)
0.6 0.5 0.4 0.3 0.2 0.1 0 0 TJ = 125C TJ = 25C TJ = -55C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT-TO-GROUND VOLTAGE (V) 4.0
0.6 0.5 0.4 0.3 0.2 0.1 0 0 7 6 4 1 3 2 5 OUTPUT-TO-GROUND VOLTAGE (V) 8 TJ = 125C TJ = 25C TJ = -55C
CURRENT (mA)
4
UW
40 45
LT1019 * TPC01
LT1019 * TPC07
Quiescent Current (LT1019-4.5/LT1019-5)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
0 5 10 25 30 35 INPUT VOLTAGE (V) 15 20 40 45
Quiescent Current (LT1019-10)
125C 25C -55C
0
0
0
5
10
15 20 25 30 35 INPUT VOLTAGE (V)
40
45
LT1019 * TPC02
LT1019 * TPC03
Load Regulation
120
TJ = 25C 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -10 -8 -6 -4 -2 0 2 4 6 8 SINKING SOURCING OUTPUT CURENT (mA) 10 LT1019-2.5 LT1019-10 LT1019-4.5/LT1019-5
Ripple Rejection
TJ = 25C 110 100 90 80 70 60 50 40 10 100 1k 10k FREQUENCY (Hz) 100k 1M LT1019-2.5 LT1019-10 LT1019-4.5 LT1019-5
LT1019 * TPC05
LT1019 * TPC06
Shunt Mode Characteristics (LT1019-5)
1.0 0.9 0.8 0.7 INPUT OPEN 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
Shunt Mode Characteristics (LT1019-10)
INPUT OPEN
TJ = 125C
TJ = 25C TJ = -55C 0 8 2 6 4 10 12 14 OUTPUT-TO-GROUND VOLTAGE (V) 16
LT1019 * TPC08
LT1019 * TPC09
LT1019
TYPICAL PERFOR A CE CHARACTERISTICS
Temp Pin Voltage
0.90 0.85
OUTPUT VOLTAGE CHANGE (V)
0.75
80 60 40 20 0 -10 -20 -30 LT1019-2.5 LT1019-5 LT1019-10
OUTPUT CAPACITOR (F)
0.80
VOLTAGE (V)
0.70 0.65 0.60 0.55 0.50 0.45 0.40 50 25 0 75 100 -50 -25 JUNCTION TEMPERATURE (C) 125
BLOCK DIAGRA
TRIM HEATER R2 LT1019-4.5, LT1019-5, LT1019-10 = 5k LT1019-2.5 = 10k 1.188V
400
APPLICATIO S I FOR ATIO
Line and Load Regulation
Line regulation on the LT1019 is nearly perfect. A 10V change in input voltage causes a typical output shift of less than 5ppm. Load regulation (sourcing current) is nearly as good. A 5mA change in load current shifts output voltage by only 100V. These are electrical effects, measured with low duty cycle pulses to eliminate heating effects. In real world applications, the thermal effects of load and line changes must be considered.
Two separate thermal effects are evident in monolithic circuits. One is a gradient effect, where power dissipation on the die creates temperature gradients. These gradients can cause output voltage shifts even if the overall temperature coefficient of the reference is zero. The LT1019, unlike previous references, specifies thermal regulation caused by die temperature gradients.The specification is 0.5ppm/ mW. To calculate the effect on output voltage, simply multiply the change in device power dissipation by the
+
-
U
W
UW
LT1019 * TPC10
Line Regulation
140 120 100 IOUT TJ = 25C 1 10
LT1019-2.5* Stability with Output Capacitance
0.1
REGION OF POSSIBLE INSTABILITY
0.01
0.001
0
5
10
15 20 25 30 INPUT VOLTAGE (V)
35
40
0.0001 20
0 10 15 20 15 10 5 5 SINK CURRENT SOURCE CURRENT OUTPUT CURRENT (mA)
LT1019 * TPC12
LT1019 * TPC11
* LT1019-4.5/LT1019-5/LT1019-10 ARE STABLE WITH ALL LOAD CAPACITANCE.
W
R1 LT1019-2.5 = 11k LT1019-4.5 = 13.9k LT1019-5 = 16k LT1019-10 = 37.1k R3 80k VIN VOUT GND
LT1019 * BD
UU
5
LT1019
APPLICATIO S I FOR ATIO
thermal regulation specification. Example: a 10V device with a nominal input voltage of 15V and load current of 5mA. Find the effect of an input voltage change of 1V and a load current change of 2mA. P (line change) = (VIN)(ILOAD) = (1V)(5mA) = 5mA VOUT = (0.5ppm/mW)(5mW) = 2.5ppm P (load change) = (ILOAD)(VIN - VOUT) = (2mA)(5V) = 10mW VOUT = (0.5ppm/mW)(10mW) = 5ppm Even though these effects are small, they should be taken into account in critical applications, especially where input voltage or load current is high. The second thermal effect is overall die temperature change. The magnitude of this change is the product of change in power dissipation times the thermal resistance (JA) of the IC package (100C/W - 150C/W). The effect on reference output is calculated by multiplying die temperature change by the temperature drift specification of the reference. Example: same conditions as above with JA = 150C/W and an LT1019 with 20ppm/C drift specification. P (line change) = 5mW VOUT = (5mW)(150C/W)(20ppm/C) = 15ppm P (load change) = 10mW VOUT = (10mW)(150C/W)(20ppm/C) = 30ppm These calculations show that thermally induced output voltage variations can easily exceed the electrical effects. In critical applications where shifts in power dissipation are expected, a small clip-on heat sink can significantly improve these effects by reducing overall die temperature change. Alternately, an LT1019A can be used with four times lower TC. If warm-up drift is of concern, these measures will also help. With warm-up drift, total device power dissipation must be considered. In the example given, warm-up drift (worst case) is equal to:
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Warm-up drift = [(VIN)(IQ) + (VIN - VOUT)(ILOAD)] [(JA)(TC)] with IQ (quiescent current) = 0.6mA, Warm-up drift = [(15V)(0.6mA) + (5V)(5mA)] [(150C/W)(25ppm/C)] = 127.5ppm Note that 74% of the warm-up drift is due to load current times input/output differential. This emphasizes the importance of keeping both these numbers low in critical applications. With heavy loads, warm-up drift can also be improved using the technique described under "Driving Loads Above 10mA" or by heat sinking. Note that line regulation is now affected by reference output impedance. R1 should have a wattage rating high enough to withstand full input voltage if output shorts must be tolerated. Even with load currents below 10mA, R1 can be used to reduce power dissipation in the LT1019 for lower warm-up drift, etc. Output Trimming Output voltage trimming on the LT1019 is nominally accomplished with a potentiometer connected from output to ground with the wiper tied to the trim pin. The LT1019 was made compatible with existing references, so the trim range is large: + 6%, - 6% for the LT1019-2.5, + 5%, - 13% for the LT1019-5, and + 5%, - 27% for the LT1019-10. This large trim range makes precision trimming rather difficult. One solution is to insert resistors in series with both ends of the potentiometer. This has the disadvantage of potentially poor tracking between the fixed resistors and the potentiometer. A second method of reducing trim range is to insert a resistor in series with the wiper of the potentiometer. This works well only for very small trim range because of the mismatch in TCs between the series resistor and the internal thin film resistors. These film resistors can have a TC as high as 500ppm/C. That same TC is then transferred to the change in output voltage: a 1% shift in output voltage causes a (500ppm)(1%) = 5ppm/C change in output voltage drift.
W
UU
LT1019
APPLICATIO S I FOR ATIO
The worst case error in initial output voltage for the LT1019 is 0.2%, so a series resistor is satisfactory if the output is simply trimmed to nominal value. The maximum TC shift expected would be 1ppm/C. Using the Temp Pin The LT1019 has a TEMP pin like several other bandgap references. The voltage on this pin is directly proportional to absolute temperature (PTAT) with a slope of 2.1mV/C. Room temperature voltage is therefore (295K)(2.1mV/C) = 620mV. Previous bandgap references have been very sensitive to any loading on the TEMP pin because it is an integral part of the reference "core" itself. The LT1019 "taps" the core at a special point which has much less effect on the reference. The relationship between TEMP pin loading and a change in reference output voltage is less than 0.05%/A, about ten times improvement over previous references. Output Bypassing The LT1019 is designed to be stable with a wide range of load currents and output capacitors. The 4.5V, 5V, and 10V devices do not oscillate under any combination of capacitance and load. The 2.5V device can oscillate when sinking currents between 1mA and 6mA for load capacitance between 400pF and 2F (see Figure 1).
TYPICAL APPLICATIO S
Wide Range Trim 5%
OUT VIN IN LT1019 TRIM GND R1 25k VOUT VIN IN LT1019 TRIM GND
LT1019 * TA03
U
If output bypassing is desired to reduce high frequency output impedance, keep in mind that loop phase margin is significantly reduced for output capacitors between 500pF and 1F if the capacitor has low ESR (Effective Series Resistance). This can make the output "ring" with transient loads. The best transient load response is obtained by deliberately adding a resistor to increase ESR as shown in Figure 1.
VIN VIN 2 TO 5 LT1019 2 TO 5 LT1019
W
U
U
U
+
+ 2F
TANTALUM (a) (b)
2F TO 10F TANTALUM
LT1019 * F01
Figure 1. Output Bypassing
Use configuration (a) if DC voltage error cannot be compromised as load current changes. Use (b) if absolute minimum peak perturbation at the load is needed. For best transient response, the output can be loaded with 1mA DC current.
Narrow Trim Range (0.2%)
OUT R2* 1.5M VOUT R1 100k
LT1019 * TA05
*INCREASE TO 4.7M FOR LT1019A (0.05%)
7
LT1019
TYPICAL APPLICATIO S
Trimming LT1019-5 Output to 5.120V
VOUT OUT IN LT1019-5 TRIM GND 41.2k 1% 5k* 1% TRIM 4.02k 1%
LT1019 * TA04
VIN
*LOW TC CERMIT
Precision 1A Current Source
15V 11.5k 1% OUT IN
5k* 8.25k 1%
LT1019-2.5 TRIM GND
2.49M 1%
LT1012
LT1019 * TA07
IOUT = 1mA ZOUT 1011
*LOW TC CERMET, TRIM RANGE = 1.5%
V + (VOUT + 2.8V) LED GLOWS IN CURRENT LIMIT (DO NOT OMIT) R1 220 8.2 2N2905 IN LT1019 OUT GND
LT1019 * TA08
8
U
Trimming LT1019-10 Output to 10.240V
VOUT OUT IN LT1019-10 TRIM GND 90.9k 1% 5k* 1% TRIM 4.02k 1%
VIN
*LOW TC CERMET
LT1019 * TA06
Negative Series Reference
V+ R1* IN D1* R2* -VREF AT 50mA
LT1019 * TA10
LT1019 OUT GND
VOUT 11V COMPLIANCE
Q1 2N2905
+
-
Output Current Boost with Current Limit
+ V - - VREF *R1 = V - 5V , R2 = , D1 = VREF + 5V 1mA 2mA
ILOAD 100mA 2F SOLID TANTALUM
LT1019
TYPICAL APPLICATIO S
Negative 10V Reference for CMOS DAC
OUT LT1019-10 TRIM GND
IOUT
REF 1.2k -15V *LOW TC CERMET, TRIM RANGE = 1.5%
SCHE ATIC DIAGRA
Q32 Q31 R20 750 Q30 R24 850 Q20 Q25 Q33 R33 1k VOUT R1 R25 1k R26 3k R28 9k R27 9k R15 3k Q4 Q5 Q6A Q6B Q18 R34 4k R17 500 Q34 R31 22k Q23 Q21 C4 R35 27k Q16 R2 R14 72k R4 R5 Q14 R29 80k TRIM R6 Q1 780 R7 1.6k Q17 Q15 Q22 Q2 C3 R19 15 R32 500 Q26
Q3
SHORT FOR 2.5
R8 2.5k
R9 3k
R36 82k Q38 Q36 R39
Q8 Q9
1k
Q37 R42 4k Q7 R38 3.75k R3 5k R37 2k R11A 1.9k R11B 1k R13 24.5k R12 7.2k
Q10 R18 2k Q11 Q12
+
-
W
U
59k 1% 5k* 5.76k 1% CMOS DAC fB 30pF VOUT
LT1007
LT1019 * TA09
W
VIN R23 100 R21 20
Q29
Q28
Q27
R16 3k Q19
Q35
Q24
Q13 HEATER
R40 400 GND
9
LT1019
PACKAGE DESCRIPTIO
SEATING PLANE 0.010 - 0.045 (0.254 - 1.143) 0.016 - 0.021 (0.406 - 0.533)
45TYP 0.027 - 0.034 (0.686 - 0.864)
0.300 - 0.320 (7.620 - 8.128)
0.009 - 0.015 (0.229 - 0.381)
(
+0.025 0.325 -0.015 8.255 +0.635 -0.381
)
10
U
Dimensions in inches (millimeters) unless otherwise noted. H Package 8-Lead TO-5 Metal Can
0.335 - 0.370 (8.509 - 9.398) DIA 0.305 - 0.335 (7.747 - 8.509) 0.040 (1.016) MAX 0.050 (1.270) MAX GAUGE PLANE 0.165 - 0.185 (4.191 - 4.699) REFERENCE PLANE 0.500 - 0.750 (12.700 - 19.050)
0.027 - 0.045 (0.686 - 1.143)
0.200 - 0.230 (5.080 - 5.842) BSC
0.110 - 0.160 (2.794 - 4.064) INSULATING STANDOFF
NOTE: LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND SEATING PLANE.
H8(5) 0592
H8 Package 8-Lead Plastic DIP
0.400 (10.160) MAX 8 7 6 5
0.250 0.010 (6.350 0.254)
1
2
3
4
0.045 - 0.065 (1.143 - 1.651)
0.130 0.005 (3.302 0.127)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.020 (0.508) MIN
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
0.018 0.003 (0.457 0.076)
N8 0392
LT1019
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic SOIC
0.189 - 0.197 (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157 (3.810 - 3.988)
1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.016 - 0.050 0.406 - 1.270 0- 8 TYP
2
3
4
0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) BSC
SO8 0392
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1019
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FRANCE Linear Technology S.A.R.L. Immeuble "Le Quartz" 58 Chemin de la Justice 92290 Chatenay Malabry France Phone: 33-1-41079555 FAX: 33-1-46314613 GERMANY Linear Technology GMBH Untere Hauptstr. 9 D-85386 Eching Germany Phone: 49-89-3197410 FAX: 49-89-3194821 JAPAN Linear Technology KK 5F YZ Bldg. Iidabashi, Chiyoda-Ku Tokyo, 102 Japan Phone: 81-3-3237-7891 FAX: 81-3-3237-8010 KOREA Linear Technology Korea Branch Namsong Building, #505 Itaewon-Dong 260-199 Yongsan-Ku, Seoul Korea Phone: 82-2-792-1617 FAX: 82-2-792-1619 SINGAPORE Linear Technology Pte. Ltd. 101 Boon Keng Road #02-15 Kallang Ind. Estates Singapore 1233 Phone: 65-293-5322 FAX: 65-292-0398 TAIWAN Linear Technology Corporation Rm. 801, No. 46, Sec. 2 Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: 886-2-521-7575 FAX: 886-2-562-2285 UNITED KINGDOM Linear Technology (UK) Ltd. The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 44-276-677676 FAX: 44-276-64851
World Headquarters
Linear Technology Corporation 1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507
06/24/93
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
LT/GP 0893 10K REV B * PRINTED IN THE USA
(c) LINEAR TECHNOLOGY CORPORATION 1993

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